The present disclosure relates to a semiconductor device, and more particularly, to a transistor in a semiconductor device, and a method of fabricating the same.
Recently, the design rule has continuously decreased as semiconductor devices have been highly integrated. The decreased design rule generally results in limitations such as short channel effect and junction leakage current. Such limitations often deteriorate the refresh characteristic of semiconductor devices. Thus, a typical method went further from the typical planar type structure and introduced diversified transistor structures including a recess type structure, a fin type structure, and a saddle fin type structure.
Fabricating the recess type transistor includes etching an active region to a certain depth and forming a gate electrode over a substrate to increase the channel length and reduce junction leakage current.
Fabricating the fin type transistor includes etching a device isolation region to a certain depth in a manner that an upper portion of an active region protrudes and forming a gate line over a substrate which intersects the active region. The upper portion of the active region vertically protruding from the surface of the device isolation region is referred to as a fin active region hereinafter. In the fin type transistor fabricated as described above, three sides of the fin active region are surrounded by the gate line, which in turn increases the channel length and improves current drivability of a memory device.
Fabricating the saddle fin type transistor includes one or more steps from the methods of fabricating both the recess type transistor and the fin type transistor described above. Thus, the channel length may be increased, junction leakage current may be reduced, and current drivability of a memory device may be improved. In the following description, a method of fabricating a typical saddle fin type transistor and related limitations are described in detail.
FIGS. 1A to 3C illustrate stages in a method of fabricating a typical saddle fin type transistor. FIGS. 1A, 2A, and 3A illustrate perspective views of a typical saddle fin type transistor. FIGS. 1B, 2B, and 3B illustrate cross-sectional views taken along a first direction A-A′ of the typical saddle fin type transistor shown in FIGS. 1A, 2A, and 3A, respectively. FIGS. 1C, 2C, and 3C illustrate cross-sectional views taken along a second direction B-B′ of the typical saddle fin type transistor shown in FIGS. 1A, 2A, and 3A, respectively.
Referring to FIGS. 1A to 1C, stages are depicted in a shallow trench isolation (STI) process performed on a substrate 100 to form device isolation regions 110. Consequently, active regions of the substrate 100 are defined.
The STI process includes forming a hard mask layer (not shown) over the substrate 100. First photoresist patterns (not shown) are formed over the hard mask layer, the first photoresist patterns having a certain spacing distance from each other and extended along the first direction A-A′.
The hard mask layer and the substrate 100 are etched to a certain depth using the first photoresist patterns as an etch barrier to form trenches. The trenches are formed to have vertical sidewalls. Thus, the trenches are formed to have a uniform width, regardless of the depth.
An insulation layer is formed over the substrate structure. A planarizing process is performed on the resulting substrate structure until a surface of the substrate 100 is exposed. As a result, the device isolation regions 110 are formed and the active regions are defined. Thus, a width of the active regions, as represented by reference denotation W1, is determined, and the active regions obtain a uniform value irrespective of the height.
Referring to FIGS. 2A to 2C, second photoresist patterns (not shown) are formed over the substrate structure. The second photoresist patterns are formed to expose a gate line region. The gate line region refers to a region where a subsequent gate line is to be formed. The gate line region is formed to intersect the active regions, extended along the second direction B-B′.
The active regions and the device isolation regions 110 are selectively etched using the second photoresist patterns as an etch barrier to form a saddle fin type structure. Reference numeral 110A represents etched device isolation regions 110A.
In more detail, portions of the active regions exposed by the second photoresist patterns are etched to a first depth D1 using the second photoresist patterns as an etch barrier to form a recess type structure. Exposed portions of the device isolation regions 110 are etched to a second depth D2 using the second photoresist patterns as an etch barrier to form a fin type structure where the etched active regions protrude in a vertical direction. Thus, the etched device isolation regions 110A are formed. The second depth D2 has a larger value than the first depth D1. Consequently, a saddle fin type structure including a recess type structure and a fin type structure is formed.
In this saddle fin type structure, reference box A1 represents fin active regions vertically protruding from a surface of the etched device isolation regions 110A. At this time, a height of the fin active regions A1 above an upper surface of the etched device isolation regions 110A is represented by reference arrow D3 and corresponds to the height difference between the first depth D1 and the second depth D2.
Referring to FIGS. 3A to 3C, a gate insulation layer 120 is formed over a portion of the substrate structure 100. A gate line 130 is formed over a gate line region. The gate line 130 includes a stack structure of a first conductive layer 130A and a second conductive layer 130B.
An impurity ion implantation process is performed on portions of the active regions on both sides of the gate line 130 to form source and drain regions.
In the above described structure, the ratio between a width W2 and a length W3 of an upper surface of the fin active regions A1 may be improved to enhance the threshold voltage (Vt) margin. In other words, the width W2 may be reduced and the length W3 may be increased.
However, the width W1 of the active regions needs to be decreased when forming the device isolation regions 110 in order to reduce the width W2 of the upper surface of the fin active regions A1. In this case, there is a limitation in that the typical profile is changed. Furthermore, if the width W2 of the fin active regions A1 is decreased, the size of the active regions also decreases. This causes another limitation in that it increases contact resistance.
Moreover, if the length W3 of the upper surface of the fin active regions A1 is increased, the possibility of a short circuit occurring during a subsequent process for forming a landing plug contact (LPC) also increases. Therefore, there are limitations as to increasing the length W3 of the fin active regions A1. Consequently, a new or improved approach to improving the ratio between the width W2 and the length W3 of the upper surface of the fin active regions A1 is believed to be beneficial.